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INTEGRATED CIRCUITS
74F173 Quad D-type flip-flop (3-State)
Product specification IC15 Data Handbook 1990 Aug 31
Philips Semiconductors
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
FEATURES
* Edge-triggered D-type register * Gated clock enable for hold "do nothing" mode * 3-state output buffers * Gated output enable control * Speed upgrade of N8T10 and current sink upgrade * Controlled output edges to minimize ground bounces * 48mA sinking capability
DESCRIPTION
The 74F173 is a high speed 4-bit parallel load register with clock enable control, 3-state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low-to-high clock (CP) transition. When one or both enable inputs are high one setup time before the low-to-high clock transition, the register retains the previous data.
TYPE 74F173 TYPICAL fmax 125MHz
Data inputs and clock enable inputs are fully edge-triggered and must be stable only one setup time before the low-to-high clock transition. The master reset (MR) is an active-high asynchronous input. When the MR is high, all four flip-flops are reset (cleared) independently of any other input condition. The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable (OE0 and OE1) inputs are low, the data in the register is presented at the Q output. When one or both OE inputs are high, the outputs are forced to a high impedance "off" state. The 3-state output buffers are completely independent of the register operation; the OE transition does not affect the clock and reset operations.
TYPICAL SUPPLY CURRENT (TOTAL) 23mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F173N N74F173D PKG DWG # SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D3 CP E0, E1 MR OE0, OE1 Q0 - Q3 Data inputs Clock input Clock enable inputs Master reset input Output enable inputs Data outputs DESCRIPTION 74F (U.L.) HIGH/ LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 750/80 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 15mA/48mA
Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
August 31, 1990
2
853-1160 00286
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
PIN CONFIGURATION
OE0 1 OE1 2 Q0 3 Q1 4 Q2 5 Q3 6 CP 7 GND 8 16 V CC 15 MR 14 D0 13 D3 12 D2 11 Q2 10 E1 9 E0
IEC/IEEE SYMBOL
9 10 7 1 2 15 14 13 12 11 R 1D 3 4 5 6 & & C1
EN
SF00290
SF00292
LOGIC SYMBOL
14 13 12 11
9 10 7 15 1 2
E0 E1 CP MR OE0 OE1
D0 D1 D2 D3
Q0 Q1 Q2 Q3
VCC = Pin 16 GND = Pin 8
3
4
5
6
SF00291
FUNCTION TABLE
INPUTS MR H L L L CP X X E0 X l l h E1 X l l X Dn X l h X OUTPUTS Qn (register) L L H qn Hold (do nothing) Reset (clear) Parallel load OUTPUTS
L X X h X qn Notes to function table H = High-voltage level h = High state one setup time before the low-to-high clock transition L = Low-voltage level l = Low state one setup time before the low-to-high clock transition qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low-to-high clock transition X = Don't care = Low-to-high clock transition
August 31, 1990
3
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
FUNCTION TABLE
INPUTS Qn (register) L H X OE0 L L H OE1 L L X H OUTPUTS Qn L H Z Z Disabled Read OUTPUTS
X X Notes to function table H = High-voltage level L = Low-voltage level X = Don't care Z = High impedance "off" state
LOGIC DIAGRAM
D0 E0 E1 9 10 14 D1 13 D2 12 D3 11
7 CP
D CP RD 15 MR OE0 OE1 1 2
Q
D CP
Q
D CP
Q
D CP
Q
Q
RD
Q RD
Q
RD
Q
3 VCC = Pin 16 GND = Pin 8 Q0
4 Q1
5 Q2
6 Q3
SF00293
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 96 0 to +70 -65 to +150 UNIT V V mA V mA
C C
August 31, 1990
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Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range 0 4.5 2.0 0.8 -18 -15 48 +70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA UNIT
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level output voltage VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOH = -15mA VOL VIK II IIH IIL IOZH IOZL IOS Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Short-circuit output current3 ICCH ICC Supply current (total) ICCL ICCZ VCC = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX -60 19 27 23 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.4 2.7 2.0 2.0 3.1 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -150 26 37 32 3.4 LIMITS TYP2 MAX V V V V V V V A A mA A A mA mA mA UNIT
mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
August 31, 1990
5
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION Waveform 1 Waveform 1 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 5 Waveform 4 VCC = +5.0V CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tTHL tTLH Maximum clock frequency Propagation delay CP to Qn Propagation delay MR to Qn Output enable time to high or low level Output disable time from high or low level Transition time 10% to 90%, 90% to 10% 100 4.5 6.0 6.5 3.5 5.5 1.5 3.0 2.0 4.0 TYP 125 6.5 8.0 8.5 5.0 7.0 3.5 5.0 5.0 7.5 9.0 10.5 11.5 8.0 10.0 7.0 8.5 8.0 10.0 MAX VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 90 4.0 5.5 6.0 2.5 4.5 1.0 2.5 2.0 4.0 10.0 11.5 12.5 8.5 11.0 8.0 9.0 8.5 11.0 MAX MHz ns ns ns ns ns Tamb = 0C to +70C UNIT
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (H) trec Setup time, high or low level Dn to CP Hold time, high or low level Dn to CP Setup time, high or low level E to CP Hold time, high or low level E to CP CP Pulse width, high or low MR Pulse width, high Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 2.5 2.5 0 0 4.5 7.5 0 0 3.0 6.0 3.5 4.5 TYP MAX VCC = +5.0V 10% CL= 50pF, RL = 500 MIN 3.0 4.0 0 0 5.0 8.5 0 0 3.0 6.0 3.5 5.5 MAX ns ns ns ns ns ns ns Tamb = 0C to +70C UNIT
AC WAVEFORMS
1/fmax CP VM tw(H) tPHL VM tw(L) tPLH VM VM VM
Qn
SF00294
Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency
August 31, 1990
6
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
MR
VM
VM trec VM tPHL
OE
VM tPZH
VM tPHZ 90% VM VOH -0.3V
tw(H) CP
Qn 10%
0V
SF00297
VM VM
Qn
Waveform 4. 3-state output enable time to high level, output disable time from high level and transition time to high level
SF00295
OE VM tPZL 90% Qn VM 10% VOL +0.3V VM tPLZ
Waveform 2. Master reset pulse width, master reset to output delay and master reset to clock recovery time
3.5V
En, Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
SF00298
CP VM VM
Waveform 5. 3-state output enable time to low level, output disable time from low level and transition time to low level
SF00296
Waveform 3. Data and enable setup time and hold times Notes to AC waveforms 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for Open Collector Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00128
August 31, 1990
7
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1990 Aug 31
8
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1990 Aug 31
9
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05088
Philips Semiconductors
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